OP07CP DIP

The OP07 has very low input offset voltage (75 uV max for OP07E) which is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP07 also features low input bias current (±4 nA for OP07E) and high open-loop gain (200 V/mV for OP07E). The low (A30)offsets and high open-loop gain make the OP07 particularly useful for high-gain instrumentation applications. (A30)